ADC raw data capture
Implementation
ADC channels must be present in the device tree as io-channels property of "zephyr,user" node, such that they are recognized
by ADC.cpp and organized in list of Oasis-style format ADC [cs] [chan].
STM32 ADC
The reading/capture/dump functions are currently only implemented on STM32 ADCs by re-using the adc_stm32 driver with slight modification:
- allow mixture of shared interrupt and dedicated interrupt for multiple ADCs on chip
- disable ADC on initialization in order to prevent soft boot hang-up
- add support for SMP table of STM32H7 ADC3
The ADC clocks for STM32 may impact sample time and needs careful design thoughts. For example on STM32H725, where the clocks are configured as:
System clock (adc_sclk): 550MHz
AHB peripheral clock (adc_hclk): 275MHz (HPRE Prescaler = "/2")
CKMODE = 11 = "adc_sclk/4" (default implementation in Zephyr driver)
SMP = 101 (64.5)
- Fadc = adc_sclk / hpre_prescaler / ckmode / 2 = 34.375MHz
- TSAMP = SMP / Fadc = 64.5 / 34.375MHz = 1.876us
- TCONV = Sampling time (SMP) + 7.5 ADC clock cycles = (SMP + 7.5) / Fadc = 2.095us
The choice of sampling time (SMP) must be guarantee that Cadc is fully charged when the channel is switched in. The analog source impedance (Rain) and input decoupling/filtering capacitor must be taken into account.