Hitless soft reset
Overview
The default implementation of sys_arch_reboot on Cortex-M platform invokes NVIC_SystemReset, which effectively performs software(SW) reset of the system. All registers are reset except the reset flags in the clock control/status register (RCC_CSR or RCC_RSR on H7) and the registers in the RTC domain (See RCC section in reference manual).
In order to keep state of output pins and status of registers, a soft/warm reset needs to be implemented. Rather than perform a system reset, a soft reset loads entry point into the PC register, which is the second word of Cortex-M vector table. In addition, interrupts must be disabled (implemented in sys_reboot as a general rule) the MSP needs to be reset.
Configurator that works in look-aside mode and shares SPI master with FPGA must not implement soft boot because that nCONFIG state is kept across boot and FPGA remains active. Consequently, initialization of SPI-NOR flash driver would fail. Even though it is technically possible to skip the flash initialization, it may not worth that as configurator never needs a reset.
A block of memory is allocated on On-chip RAM for persistence of reset information (class, bank and cause). Since the RAM content persists across system reset, it can be used for reset management.
A simple dual-bank bootloader is implemented to select firmware image banks. When power-on (or hard) reset is detected, the bootloader wipe out the entire persist memory, and try selecting the up-to-date firmware image bank. The bootloader clears requested bank and sets actual bank. If invalid requested bank is detected, auto bank selection is attempted.
For NIOS2 processor, Zephyr does not provide implementation of sys_arch_reboot. A similar jump-entry mechanism has been implemented.
Many QEMU targets have override sys_arch_reboot in SOC. Therefore, warm boot is not implemented for QEMU targets.
GPIO
State of GPIO output need to be sampled by gpio_pin_get_dt API before reconfiguring using the gpio_pin_configure_dt API. Care must be taken of the ACTIVE_LOW pins where in inversion configuration is not recognized on sampling. Currently there is no generic architecture of GPIO pin state management. The pin state must be reconfigured individually as needed.
Timing
A brief timing test has been made on STM32G474 eval board. SystemReady pin needs to configured in the device tree. The minimal firmware de-asserts SystemReady in boot command handler, and asserts SystemReady when all tasks are started.
- Soft reset: 2ms
- Hard reset: 10ms