PWM control prototype on STM32 MCU

Design

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The Oasis-style PWM drive is designed as a virtual DAC interface. In order to unify interface for various DAC, a DAC-PWM driver is implemented instead of using the existing PWM API. A DAC-PWM also has benefits that PWM behavior during Warm/NTA reset can be customized. DAC outputs are cached for retrieval across soft reset if persist RAM is defined.

Period optimization

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Oasis PWM's period is fixed at 256 cycles. This means 1/256 resolution applies to the entire range. For logarithm applications, the fixed period/resolution results in large errors in dB scale at small counts. This can be optimized by fine tune the period with an offset proportional to the quantization error. Refer to sample code $1 for more details. This approach is not applicable to PWMs that share GP timer on STM32 as the ARR register (period) is shared, i.e. only TIM13,14,16,17 are free for use with this approach while others must be used with cautions.

Reference design

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[1] B-G474E-DPOW1 documentation