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Fast control loop prototype on STM32 MCU

Design

Fast control loop aims at time critical control applications where instantaneous response to changes of data inputs is required. A common implementation is fast ISR (a.k.a. FISR) of timer interrupt on a fixed interval. Since timer peripherals are different among SOCs or even within a SOC, it is designed with device driver support.

Implementation

  • On many ARM MCUs, Zephyr allows zero latency interrupts which offsets system-wide interrupt priorities by a reserved level. When this feature is enabled (by CONFIG_ZERO_LATENCY_IRQS), FISR runs at highest priority group and preempts other low priority ISRs. The default CONFIG_ZERO_LATENCY_LEVELS is 1 which works on most ARM CPUs. However, there are at least two IRQ levels in one priority group on STM32H7, the CONFIG_ZERO_LATENCY_LEVELS must be set to 2 in order to offset system-wide IRQs into lower priority groups. Notice that Cortex-M0/M0+ MCUs do not support zero latency interrupts.
  • Other than enabling zero latency interrupts, direct isr can be used to minimize interrupt latency. A direct ISR is defined in device tree and must be unique in the system (attached to one timer).
  • Relocating ISR code into STM32 CCM or ITCM can reduce interrupt latency further. Currently direct FISR is put into CCM/ITCM once they are detected. DTCM could also be used for variables/buffers to be processed by direct FISR.
  • Calling driver APIs (e.g. ADC or GPIO) would introduce overheads of call/ret. It is suggested to directly access registers for very fast control loop to remove unnecessary cycles.

FISR benchmark

A simple benchmark is made to measure latency of FISR and execution cycles within FISR. Typical latency on Cortex-M4/M7 ranges from 30 to 50 cycles. Execution cycles prove to determined for zero latency interrupts as they are not preempted by system-wide interrupts.

由 Victor Chen 编辑于