Zephyr on RISC-V and NIOS-II softcore
Initial porting work on RISCV and NIOS2
SOC and board porting tips
- Customized SOC porting files should to be added to
zoysia/soc/${ARCH}/*/<soc_name>directory. A soft-link inzephyr/soc/${ARCH}/*/<soc_name>should to be created correspondingly. Be aware that the soft-link is ignored by .gitignore rules. - Device tree file
zoysia/dts/<soc_name>.dtsishould to be added to describe the SOC, and create DTS bindings if necessary. - SOC peripheral driver implementations should to be added to
zoysia/drivers/* - Board files should be added to
zoysia/boards/${ARCH}/<board_name> - Board overlays and Kconfig customization should be put into
apps/zoysia/boards (freestanding projects)
Timer
RTOS ticks come periodic triggering from a timer peripheral of SOC. The original plan was to make existing Oasis timestamp IP as a general design for both NIOS2 and RISC-V. However, RISC-V's privileged ISA has a complete definition of timer (a.k.a. mtime) as well as interrupt/trap architecture. For SOC that follows ISA spec, it would make more sense to use common timer design. On the other hand for NIOS2 port, it sounds reasonable to use Intel's timer IP to replace Oasis timestamp for Zephyr application. However, the driver does not provide high resolution timestamp, so Oasis timer IP is still the best fit.
UART
The demo project of NIOS2 on Max10 uses 16650 UART driver with 64-bytes depth FIFO. However this UART IP requires extra license, so Oasis UART driver will be used for NIOS2 ports. For Sapphire/Saxon, the SOC's UART needs driver development.
Flash
Oasis flash driver is ported to Zephyr with a few changes and now supports multiple device now. The task-woken-by-ISR function is implemented by a semaphore. The Bootrom block is listed on the flash map with Addr() access only.